I. Field of the Invention
The present invention relates to a semiconductor package and a method for fabricating the semiconductor package.
II. Description of the Prior Art
Recently, semiconductor devices have been developed to have a thinner and more miniature structure. For such semiconductor devices, there are ball grid array (BGA) semiconductor packages, chip scale semiconductor packages, and micro BGA semiconductor packages.
Also, semiconductor chips, which are mounted on semiconductor packages as mentioned above, have been developed toward a high performance of electric power circuits, an increase in operating frequency, and an expansion of circuit functions, in pace with the development of integration techniques and manufacturing equipment. For this reason, an increase in heat occurs inevitably during the operation of such a semiconductor chip.
Referring to FIG. 10, a typical BGA semiconductor package having a conventional structure involving the above mentioned problem is illustrated.
As shown in FIG. 10, the BGA semiconductor package, which is denoted by the reference numeral 100xe2x80x2, includes a semiconductor chip 1xe2x80x2 arranged at a central portion of the semiconductor package 100xe2x80x2. The semiconductor chip 1xe2x80x2 is provided with a plurality of integrated electronic circuits. A plurality of input/output pads 2xe2x80x2 are provided at an upper surface of the semiconductor chip 1xe2x80x2. A circuit board 10xe2x80x2 is bonded at a central portion thereof to a lower surface of the semiconductor chip 1xe2x80x2 by means of an adhesive 3xe2x80x2.
The circuit board 10xe2x80x2 includes a resin substrate 15xe2x80x2. A circuit pattern 12xe2x80x2 provided with bond fingers 11xe2x80x2 is formed on an upper surface of the resin substrate 15xe2x80x2 around the semiconductor chip 1xe2x80x2. Another circuit pattern provided with a plurality of ball lands 13xe2x80x2 is formed on a lower surface of the resin substrate 15xe2x80x2. Each of the circuit patterns is comprised of a thin film made of a conductive material such as copper (Cu). These circuit patterns are interconnected together by via holes 14xe2x80x2. The exposed surface portions of the circuit patterns not covered with the bond fingers 11xe2x80x2 and ball lands 13xe2x80x2 are coated with cover coats 16xe2x80x2, respectively, so that those circuit patterns are protected from the external environment.
The input/output pads 2xe2x80x2 of the semiconductor chip 1xe2x80x2 are connected to the bond fingers 11xe2x80x2 on the upper surface of the circuit board 10xe2x80x2 by means of conductive wires 4xe2x80x2, respectively. In order to protect the conductive wires 4xe2x80x2 from the external environment, the upper surface of the circuit board 10xe2x80x2 is encapsulated by a resin encapsulate 20xe2x80x2.
The circuit board 10xe2x80x2 is mounted on a mother board (not shown) in a state in which a plurality of conductive balls 40xe2x80x2 are fused on the ball lands 13xe2x80x2, respectively, so that it serves as a medium for electrical signals between the semiconductor chip 1xe2x80x2 and mother board.
In the BGA semiconductor package 100xe2x80x2 having the above mentioned configuration, the semiconductor chip 1xe2x80x2 thereof exchanges electrical signals with the mother board via the input/output pads 2xe2x80x2, conductive wires 4xe2x80x2, bond fingers 11xe2x80x2, via holes 14xe2x80x2, ball lands 13xe2x80x2, and conductive balls 40xe2x80x2, respectively.
However, the above mentioned conventional BGA semiconductor package is problematic in that it has an increased thickness because the semiconductor chip is bonded to the upper surface of the circuit board having a relatively large thickness. This is contrary to the recent trend toward a miniaturization and thinness. As a result, the above mentioned semiconductor package is problematic in that it cannot be applied to a variety of miniature electronic appliances such as portable phones, cellular phones, pagers, and notebooks.
Furthermore, in spite of the increasing heat generated at the semiconductor chip, as mentioned above, there is no appropriate heat discharge means in the conventional semiconductor package. As a result, the conventional semiconductor package is implicated in a heat-related degradation in the electrical performance and other functions of the semiconductor chip. In severe cases, the semiconductor package and the electronic appliance using it may be so damaged as not to be inoperable.
Although a semiconductor package has been proposed, which is provided with a heat discharge plate or heat sink for easily discharging heat generated from the semiconductor chip, the provision of such a heat discharge plate causes another problem because it serves to further increase the thickness of the semiconductor package while increasing the manufacturing costs.
Therefore, the present invention has been made in view of the above mentioned problems involved in the prior art, and an object of the invention is to provide a semiconductor package having a super-thin structure and a method for fabricating the semiconductor package.
Another object of the invention is to provide a semiconductor package having a structure capable of easily discharging heat from a semiconductor chip included therein, and a method for fabricating the semiconductor package.
In accordance with one aspect, the present invention provides a semiconductor package comprising: a semiconductor chip having a first major surface and a second major surface, the semiconductor chip being provided at the second major surface with a plurality of input/output pads; a circuit board including a resin substrate having a first major surface and a second major surface, a first circuit pattern formed at the first major surface and provided with a plurality of ball lands, a second circuit pattern formed at the second major surface and provided with a plurality of bond fingers connected with the ball lands by conductive via holes, cover coats respectively coating the first and second circuit patterns while allowing the bond fingers and the ball lands to be open, and a central through hole adapted to receive the semiconductor chip therein; electrical connection means for electrically connecting the input/output pads of the semiconductor chip with the bond fingers of the circuit board, respectively; a resin encapsulate for encapsulating the semiconductor chip, the electrical connection means, and the circuit board; and a plurality of conductive balls fused on the ball lands of the circuit board, respectively.
The semiconductor chip may be arranged in such a fashion that it is oriented, at the second major surface thereof, in the same direction as the second major surface of the circuit board provided with the bond fingers while being flush, at the first major surface thereof, with the first major surface of the circuit board provided with the ball lands and one surface of the resin encapsulate.
The resin encapsulate may be formed to completely or partially encapsulate the second major surface of the circuit board provided with the bond fingers.
The second major surface of the circuit board provided with the bond fingers may be further provided with a plurality of ball lands.
A plurality of conductive balls may be fused on the ball lands provided at the second major surface of the circuit board, respectively.
The semiconductor package may further comprises a closure member attached to the first major surface of the semiconductor chip and adapted to cover the through hole of the circuit board.
Preferably, each of the closure members comprises an insulating tape or a copper layer.
In accordance with another aspect, the present invention provides a method for fabricating semiconductor packages comprising the steps of: preparing a circuit board strip including a plurality of unit circuit boards, the circuit board strip having a plurality of ball lands formed at a first major surface thereof, a plurality of bond fingers formed at a second major surface thereof and respectively connected with the ball lands by conductive via holes, and a plurality of through holes respectively associated with the unit circuit boards; receiving, in the through holes, semiconductor chips each having a first major surface and a second major surface provided with a plurality of input/output pads, respectively; electrically connecting the input/output pads of the semiconductor chips with associated ones of the bond fingers of the circuit board strip using connection means, respectively; encapsulating the semiconductor chips, the connection means, and the through holes of the circuit board strip using an encapsulating material; fusing conductive balls on the ball lands of the circuit board strip; and singulating the circuit board strip into semiconductor packages respectively corresponding to the unit circuit boards.
The circuit board strip prepared at the circuit board strip preparing step may comprise: a main strip including a resin substrate having a substantially rectangular strip shape provided with a first major surface and a second major surface; a plurality of main slots extending to a desired length in a direction transverse to a longitudinal direction of the main strip while being uniformly spaced apart from one another in the longitudinal direction of the main strip, thereby dividing the main strip into a plurality of sub-strips aligned together in the longitudinal direction of the main strip; a plurality of sub slots extending to a desired length and serving to divide each of the sub-strips into a plurality of strip portions arranged in a matrix array, each of the strip portions corresponding to one of the unit circuit boards while having one of the through holes; a plurality of first circuit patterns each formed on the first major surface of the resin substrate for an associated one of the strip portions and provided with associated ones of the ball lands; a plurality of second circuit patterns each formed on the second major surface of the resin substrate for an associated one of the strip portions and provided with associated ones of the bond fingers; and cover coats respectively coated over the first and second major surfaces of the resin substrate while allowing the bond fingers and the ball lands to be externally open.
Alternatively, the circuit board strip prepared at the circuit board strip preparing step may comprise: a resin substrate having a substantially rectangular strip shape provided with a first major surface and a second major surface; a plurality of slots extending to a desired length and serving to divide each of the resin substrate into a plurality of substrate portions arranged in a matrix array, each of the substrate portions corresponding to one of the unit circuit boards while having one of the through holes; a plurality of first circuit patterns each formed on the first major surface of the resin substrate for an associated one of the strip portions and provided with associated ones of the ball lands; a plurality of second circuit patterns each formed on the second major surface of the resin substrate for an associated one of the strip portions and provided with associated ones of the bond fingers; and cover coats respectively coated over the first and second major surfaces of the resin substrate while allowing the bond fingers and the ball lands to be externally open.
The method may further comprise the step of attaching a plurality of closure members to the first major surface of the circuit board strip in such a fashion that each of the closure members covers an associated one of the through holes, prior to the step of receiving the semiconductor chips in the through holes.
The method may further comprise the step of attaching a plurality of closure members to the first major surface of the main strip in such a fashion that each of the closure members covers an associated one of the through holes, prior to the step of receiving the semiconductor chips in the through holes.
The closure member attaching step may comprise the steps of preparing closure member strips each having closure members for an associated one of the sub-strips, and individually attaching the closure member strips to the sub-strips, respectively, in such a fashion that each of the closure member strips is arranged to cover the main slot formed at one side of an associated one of the sub-strips.
Alternatively, the closure member attaching step may comprise the steps of preparing a single closure member strip having closure members for all sub-strips of the circuit board strip while having small singulation apertures at a region corresponding to each of the main slots, and attaching the closure member strip to the main strip in such a fashion that the closure member strip is arranged to allow each of the small singulation apertures to be aligned with an associated one of the main slots.
The closure members are removed after the encapsulating step, e.g., before or after the conductive ball fusing step, or after the singulation step.
The closure members may be removed by inserting a planar bar into each of the main slots in a direction from the second major surface of the circuit board strip to the first major surface of the second board strip, thereby detaching an associated one of the closure members from the circuit board strip at one side of the associated closure member.
Each of the closure members may comprise an insulating tape, an ultraviolet tape, or a copper layer.
The encapsulating step may be carried out to form an encapsulate completely encapsulating the second major surface of the circuit board strip.
The singulation step may be carried out in such a fashion that the encapsulate and the circuit board strip are simultaneously singulated.
The encapsulating step may comprise the steps of interposing the circuit board strip between a pair of molds, one of which has cavities and gates, in such a fashion that the second major surface of each of the semiconductor chips faces an associated one of the cavities while facing an associated one of the gates at a central portion thereof, and injecting the encapsulating material into each of the cavities through an associated one of the gates in such a fashion that it flows outwardly from the central portion of the second major surface of the associated semiconductor chip along the second major surface.
The circuit board strip prepared at the circuit board strip preparing step may be further provided with a plurality of ball lands at the second major surface thereof having the bond fingers. In this case, the conductive ball fusing step further comprises the step of fusing a plurality of conductive balls on the ball lands provided at the second major surface of the circuit board strip having the bond fingers.
In accordance with the present invention, a circuit board is used which has a through hole of a desired size adapted to receive a semiconductor chip, thereby allowing the thickness of the semiconductor chip to be offset by the thickness of the circuit board. Accordingly, it is possible to fabricate semiconductor packages having a super-thin structure.
In accordance with the present invention, the semiconductor chip is outwardly exposed at one major surface thereof without being encapsulated by an encapsulate. Accordingly, heat generated from the semiconductor chip can be easily discharged into the atmosphere. This results in an improvement in the thermal and electrical performance of the semiconductor chip.
In accordance with the present invention, the circuit board may be completely encapsulated at one major surface thereof by an encapsulate. In this case, it is possible to effectively prevent a bending phenomenon of the circuit board.
In addition, the use of closure members during the fabrication of semiconductor packages according to the present invention achieves an easy encapsulating process. For such closure members, closure member strips may be used, each of which has closure members for one sub strip of a circuit board strip. In this case, the closure member strips are individually attached to the sub-strips of the circuit board strip. Alternatively, a single closure member strip may be used which has closure members for all sub-strips of the circuit board strip while having small singulation apertures or slits. By virtue of such a single closure member strip or closure member strips, an easy removal of closure members is achieved.
Also, the encapsulating process involved in the fabrication of semiconductor packages is conducted in such a fashion that it proceeds from the second major surface of each semiconductor chip in accordance with the present invention. Accordingly, it is possible to achieve a uniform encapsulation while suppressing the occurrence of a wire sweeping phenomenon.